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Freescale Semiconductor /MKL28Z7 /NVIC0 /NVIC0_ICER

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Interpret as NVIC0_ICER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CLRENA0 0 (0)CLRENA1 0 (0)CLRENA2 0 (0)CLRENA3 0 (0)CLRENA4 0 (0)CLRENA5 0 (0)CLRENA6 0 (0)CLRENA7 0 (0)CLRENA8 0 (0)CLRENA9 0 (0)CLRENA10 0 (0)CLRENA11 0 (0)CLRENA12 0 (0)CLRENA13 0 (0)CLRENA14 0 (0)CLRENA15 0 (0)CLRENA16 0 (0)CLRENA17 0 (0)CLRENA18 0 (0)CLRENA19 0 (0)CLRENA20 0 (0)CLRENA21 0 (0)CLRENA22 0 (0)CLRENA23 0 (0)CLRENA24 0 (0)CLRENA25 0 (0)CLRENA26 0 (0)CLRENA27 0 (0)CLRENA28 0 (0)CLRENA29 0 (0)CLRENA30 0 (0)CLRENA31

CLRENA2=0, CLRENA31=0, CLRENA24=0, CLRENA29=0, CLRENA20=0, CLRENA14=0, CLRENA4=0, CLRENA6=0, CLRENA3=0, CLRENA5=0, CLRENA23=0, CLRENA10=0, CLRENA17=0, CLRENA22=0, CLRENA12=0, CLRENA15=0, CLRENA1=0, CLRENA21=0, CLRENA19=0, CLRENA0=0, CLRENA30=0, CLRENA9=0, CLRENA18=0, CLRENA7=0, CLRENA26=0, CLRENA16=0, CLRENA28=0, CLRENA11=0, CLRENA8=0, CLRENA25=0, CLRENA13=0, CLRENA27=0

Description

Interrupt Clear Enable Register

Fields

CLRENA0

DMA0 channel 0/4 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA0 channel 0/4 transfer complete interrupt disabled

1 (1): write: disable DMA0 channel 0/4 transfer complete interrupt; read: DMA0 channel 0/4 transfer complete interrupt enabled
CLRENA1

DMA0 channel 1/5 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA0 channel 1/5 transfer complete interrupt disabled

1 (1): write: disable DMA0 channel 1/5 transfer complete interrupt; read: DMA0 channel 1/5 transfer complete interrupt enabled
CLRENA2

DMA0 channel 2/6 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA0 channel 2/6 transfer complete interrupt disabled

1 (1): write: disable DMA0 channel 2/6 transfer complete interrupt; read: DMA0 channel 2/6 transfer complete interrupt enabled
CLRENA3

DMA0 channel 3/7 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA0 channel 3/7 transfer complete interrupt disabled

1 (1): write: disable DMA0 channel 3/7 transfer complete interrupt; read: DMA0 channel 3/7 transfer complete interrupt enabled
CLRENA4

CTI0 or DMA0 error interrupt clear-enable bit

0 (0): write: no effect; read: CTI0 or DMA0 error interrupt disabled

1 (1): write: disable CTI0 or DMA0 error interrupt; read: CTI0 or DMA0 error interrupt enabled
CLRENA5

FLEXIO0 interrupt clear-enable bit

0 (0): write: no effect; read: FLEXIO0 interrupt disabled

1 (1): write: disable FLEXIO0 interrupt; read: FLEXIO0 interrupt enabled
CLRENA6

Timer/PWM module 0 interrupt clear-enable bit

0 (0): write: no effect; read: Timer/PWM module 0 interrupt disabled

1 (1): write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
CLRENA7

Timer/PWM module 1 interrupt clear-enable bit

0 (0): write: no effect; read: Timer/PWM module 1 interrupt disabled

1 (1): write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
CLRENA8

Timer/PWM module 2 interrupt clear-enable bit

0 (0): write: no effect; read: Timer/PWM module 2 interrupt disabled

1 (1): write: disable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
CLRENA9

Low Power Periodic Interrupt Timer interrupt clear-enable bit

0 (0): write: no effect; read: Low Power Periodic Interrupt Timer interrupt disabled

1 (1): write: disable Low Power Periodic Interrupt Timer interrupt; read: Low Power Periodic Interrupt Timer interrupt enabled
CLRENA10

Serial Peripheral Interface 0 interrupt clear-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

1 (1): write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
CLRENA11

Serial Peripheral Interface 1 interrupt clear-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 1 interrupt disabled

1 (1): write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
CLRENA12

LPUART0 status and error interrupt clear-enable bit

0 (0): write: no effect; read: LPUART0 status and error interrupt disabled

1 (1): write: disable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
CLRENA13

LPUART1 status and error interrupt clear-enable bit

0 (0): write: no effect; read: LPUART1 status and error interrupt disabled

1 (1): write: disable LPUART1 status and error interrupt; read: LPUART1 status and error interrupt enabled
CLRENA14

Inter-Integrated Circuit 0 interrupt clear-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
CLRENA15

Inter-Integrated Circuit 0 interrupt clear-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
CLRENA16

Reserved iv 32 interrupt clear-enable bit

0 (0): write: no effect; read: Reserved iv 32 interrupt disabled

1 (1): write: disable Reserved iv 32 interrupt; read: Reserved iv 32 interrupt enabled
CLRENA17

PORTA Pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTA Pin detect interrupt disabled

1 (1): write: disable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
CLRENA18

PORTB Pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTB Pin detect interrupt disabled

1 (1): write: disable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled
CLRENA19

PORTC Pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTC Pin detect interrupt disabled

1 (1): write: disable PORTC Pin detect interrupt; read: PORTC Pin detect interrupt enabled
CLRENA20

PORTD Pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTD Pin detect interrupt disabled

1 (1): write: disable PORTD Pin detect interrupt; read: PORTD Pin detect interrupt enabled
CLRENA21

PORTE Pin detect interrupt clear-enable bit

0 (0): write: no effect; read: PORTE Pin detect interrupt disabled

1 (1): write: disable PORTE Pin detect interrupt; read: PORTE Pin detect interrupt enabled
CLRENA22

Low Leakage Wakeup 0 interrupt clear-enable bit

0 (0): write: no effect; read: Low Leakage Wakeup 0 interrupt disabled

1 (1): write: disable Low Leakage Wakeup 0 interrupt; read: Low Leakage Wakeup 0 interrupt enabled
CLRENA23

Integrated interchip sound 0 interrupt clear-enable bit

0 (0): write: no effect; read: Integrated interchip sound 0 interrupt disabled

1 (1): write: disable Integrated interchip sound 0 interrupt; read: Integrated interchip sound 0 interrupt enabled
CLRENA24

Universal Serial Bus interrupt clear-enable bit

0 (0): write: no effect; read: Universal Serial Bus interrupt disabled

1 (1): write: disable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled
CLRENA25

Analog-to-Digital Converter 0 interrupt clear-enable bit

0 (0): write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

1 (1): write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
CLRENA26

Low-Power Timer interrupt clear-enable bit

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
CLRENA27

RTC seconds interrupt clear-enable bit

0 (0): write: no effect; read: RTC seconds interrupt disabled

1 (1): write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled
CLRENA28

INTMUX0 channel 0 interrupt interrupt clear-enable bit

0 (0): write: no effect; read: INTMUX0 channel 0 interrupt interrupt disabled

1 (1): write: disable INTMUX0 channel 0 interrupt interrupt; read: INTMUX0 channel 0 interrupt interrupt enabled
CLRENA29

INTMUX0 channel 1 interrupt interrupt clear-enable bit

0 (0): write: no effect; read: INTMUX0 channel 1 interrupt interrupt disabled

1 (1): write: disable INTMUX0 channel 1 interrupt interrupt; read: INTMUX0 channel 1 interrupt interrupt enabled
CLRENA30

INTMUX0 channel 2 interrupt interrupt clear-enable bit

0 (0): write: no effect; read: INTMUX0 channel 2 interrupt interrupt disabled

1 (1): write: disable INTMUX0 channel 2 interrupt interrupt; read: INTMUX0 channel 2 interrupt interrupt enabled
CLRENA31

INTMUX0 channel 3 interrupt interrupt clear-enable bit

0 (0): write: no effect; read: INTMUX0 channel 3 interrupt interrupt disabled

1 (1): write: disable INTMUX0 channel 3 interrupt interrupt; read: INTMUX0 channel 3 interrupt interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data